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  1. /*
  2.     File:        OHCIFWIM.h
  3.  
  4.     Contains:    Definitions for TI PCI-OHCI 1394 card FireWire interface module.
  5.  
  6.     Version:    1.0
  7.  
  8.     Written by:    Jay Lloyd
  9.  
  10.     Copyright:    © 1997-1998 by Apple Computer, Inc., all rights reserved.
  11.  
  12.     File Ownership:
  13.  
  14.         DRI:                Jay Lloyd
  15.  
  16.         Other Contact:        Eric Anderson
  17.  
  18.         Technology:            FireWire
  19.  
  20.     Writers:
  21.  
  22.         (jkl)    Jay Lloyd
  23.  
  24.     Change History (most recent first):
  25.  
  26.        <FW8>     9/25/98    jkl        Removed skip address from DMABuildState structure.
  27.        <FW7>     8/26/98    jkl        Cleaned up fwim data structure.
  28.        <FW6>      8/7/98    jkl        Added isochRxDummyQuadPhys field to fwim data to use in handling
  29.                                     initial time stamp quad in isoch receive header.
  30.        <FW5>      8/5/98    jkl        Added some more isoch defines.
  31.        <FW4>      8/4/98    jkl        More define and structure clean up.
  32.        <FW3>     7/28/98    jkl        Cleaned up some more defines.
  33.        <FW2>     7/27/98    jkl        Clean up naming.
  34.        <FW1>     7/24/98    jkl        first checked in
  35.  
  36. */
  37.  
  38. #ifndef __OHCIFWIM__
  39. #define __OHCIFWIM__
  40.  
  41. #ifndef __TYPES__
  42. #include <Types.h>
  43. #endif
  44. #ifndef __INTERRUPTS__
  45. #include <Interrupts.h>
  46. #endif
  47.  
  48. #ifdef __cplusplus
  49. extern "C" {
  50. #endif
  51.  
  52. #if PRAGMA_IMPORT_SUPPORTED
  53. #pragma import on
  54. #endif
  55.  
  56. #if PRAGMA_ALIGN_SUPPORTED
  57. #pragma options align=power
  58. #endif
  59.  
  60. /*zzz*/
  61. /* Isn't this PCI standard stuff?  Shouldn't it be in some regular include */
  62. /* file like PCI.h? */
  63.  
  64. #define bit0            0x00000001
  65. #define bit1            0x00000002
  66. #define bit2            0x00000004
  67. #define bit3            0x00000008
  68. #define bit4            0x00000010
  69. #define bit5            0x00000020
  70. #define bit6            0x00000040
  71. #define bit7            0x00000080
  72. #define bit8            0x00000100
  73. #define bit9            0x00000200
  74. #define bit10            0x00000400
  75. #define bit11            0x00000800
  76. #define bit12            0x00001000
  77. #define bit13            0x00002000
  78. #define bit14            0x00004000
  79. #define bit15            0x00008000
  80. #define bit16            0x00010000
  81. #define bit17            0x00020000
  82. #define bit18            0x00040000
  83. #define bit19            0x00080000
  84. #define bit20            0x00100000
  85. #define bit21            0x00200000
  86. #define bit22            0x00400000
  87. #define bit23            0x00800000
  88. #define bit24            0x01000000
  89. #define bit25            0x02000000
  90. #define bit26            0x04000000
  91. #define bit27            0x08000000
  92. #define bit28            0x10000000
  93. #define bit29            0x20000000
  94. #define bit30            0x40000000
  95. #define bit31            0x80000000
  96.  
  97.  
  98. /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
  99.  * Configuration Registers
  100.  *
  101.  */
  102. enum {
  103.     kConfigStart        = 0x00,
  104.     cwVendorID            = 0x00,
  105.     cwDeviceID            = 0x02,
  106.     cwCommand            = 0x04,
  107.     cwStatus            = 0x06,
  108.     clClassCodeAndRevID    = 0x08,
  109.     clHeaderAndLatency    = 0x0C,
  110.     clBaseAddressZero    = 0x10,            /* I/O Base address                            */
  111.     clBaseAddressOne    = 0x14,            /* Memory Base address                        */
  112.     clExpansionRomAddr    = 0x30,
  113.     clLatGntIntPinLine    = 0x3C,            /* Max_Lat, Max_Gnt, Int. Pin, Int. Line    */
  114.     cbGPIOzero            = 0xFC,            /* General Purpose Input/Output    Control        */
  115.     cbGPIOone            = 0xFD,            /* General Purpose Input/Output    Control        */
  116.     cbGPIOtwo            = 0xFE,            /* General Purpose Input/Output    Control        */
  117.     cbGPIOthree            = 0xFF,            /* General Purpose Input/Output    Control        */
  118.     kConfigEnd            = 0x100
  119. };
  120.  
  121. /*
  122.  * 0x04 cwCommand                    Command Register (read/write)
  123.  */
  124. enum {
  125.     cwCommandSERREnable            = bit8,
  126.     cwCommandEnableParityError    = bit6,
  127.     cwCommandEnableBusMaster    = bit2,        /* Set this on initialization            */
  128.     cwCommandEnableMemorySpace    = bit1,        /* Respond at Base Address One if set    */
  129.     cwCommandEnableIOSpace        = bit0        /* Respond at Base Address Zero if set    */
  130. };
  131.  
  132. /*
  133.  * 0x06 cwStatus                    Status Register (read/write)
  134.  */
  135. enum {
  136.     cwStatusDetectedParityError    = bit15,    /* Detected from slave                    */
  137.     cwStatusSignaledSystemError = bit14,    /* Device asserts SERR/ signal            */
  138.     cwStatusMasterAbort             = bit13,    /* Master sets when transaction aborts    */
  139.     cwStatusReceivedTargetAbort    = bit12,    /* Master sets when target-abort        */
  140.     cwStatusDEVSELTimingMask    = (bit10 | bit9),    /* DEVSEL timing encoding R/O    */
  141.     cwStatusDEVSELFastTiming    = 0,
  142.     cwStatusDEVSELMediumTiming    = bit9,
  143.     cwStatusDEVSELSlowTiming    = bit10,
  144.     cwStatusDataParityReported    = bit8
  145. };
  146.  
  147.  
  148. /*
  149.  * 0xFC cbGPIOzero                    GPIO zero control register (read/write)
  150.  */
  151. enum {
  152.     DISABLE_BMC                    = bit7,        // Disable Bus Manager Contender
  153.     GPIO_INV0                    = bit5,        // Polarity Invert
  154.     GPIO_ENB0                    = bit4,        // Output Enable control
  155.     GPIO_DATA0                    = bit0        // data when Disable_BMC is 1
  156. };
  157.  
  158. ////////////////////////////////////////////////////////////////////////////////
  159. //
  160. // Useful macro defs.
  161. //
  162.  
  163. #define EndianSwapImm32Bit(data32)                    \
  164. (                                                    \
  165.     (((UInt32) data32) >> 24)                |        \
  166.     ((((UInt32) data32) >> 8) & 0xFF00)        |        \
  167.     ((((UInt32) data32) << 8) & 0xFF0000)    |        \
  168.     (((UInt32) data32) << 24)                        \
  169. )
  170.  
  171. #define OHCIBitRange(start, end)                    \
  172. (                                                    \
  173.     ((((UInt32) 0xFFFFFFFF) << (31 - (end))) >>        \
  174.      ((31 - (end)) + (start))) <<                    \
  175.     (start)                                            \
  176. )
  177.  
  178. #define OHCIBitRangePhase(start, end)                \
  179.     (start)
  180.  
  181.  
  182.  
  183. ////////////////////////////////////////////////////////////////////////////////
  184. //
  185. // FWIM data defs.
  186. //
  187.  
  188. enum
  189. {
  190.     kPacketBufferSize                = 4096,    // Needs to be large enough for largest asynch packet size and multiple of 32
  191.     kEndRxDMABufferSize                = 2028,    // Last receive buffer is 4096, but only request 2028, rest is used for contiguous space
  192.     kSelfIDBufferSize                = 2048,    // Maximum self-ids we could receive is 2k
  193.     kConfigROMBufferSize            = 1024,    // Size of physically mapped config ROM memory
  194.     kAsynchQuadReadReqSize            = 16,    // 4 quads, size of asynch quadlet read request packet including header and trailer, no crc's
  195.     kAsynchBlockWriteReqHeaderSize    = 16,    // 4 quads, size of asynch block write request packet header
  196.     kAsynchQuadWriteReqSize            = 20,    // 5 quads, size of asynch quadlet write request packet including header and trailer, no crc's
  197.     kAsynchBlockReadReqSize            = 20,    // 5 quads, size of asynch block read request packet including header and trailer, no crc's
  198.  
  199.     kAsynchTxDescriptorBlockSize    = 128,    // Maximum size of a descriptor block
  200.     kNumAsynchTxDMADescriptorBlocks    = 16,    // Number of descriptors for transmit DMA
  201.                                             // 8 for requests, 8 for responses
  202.     kMaxBufPages                    = 6,    // Max # of physical pages per packet
  203.     kAsynchReqTxDMA                    = 0,    // asynch transmit request DMA index
  204.     kAsynchResTxDMA                    = 8,    // asynch transmit response DMA index
  205.  
  206. // JKL *** fix these numbers to determine a good balance between performance and memory
  207.     kAsynchRxBufs                    = 60,    // # of Asynch bufs
  208.     kAsynchResRxFirstDMA            = 0,    // First asynch receive response packet DMA index.
  209.     kAsynchResRxLastDMA                = 39,    // Last asynch receive response packet DMA index.
  210.     kAsynchReqRxFirstDMA            = 40,    // First asynch receive request packet DMA index.
  211.     kAsynchReqRxLastDMA                = 59,    // Last asynch receive request packet DMA index.
  212.  
  213.     kFWIMProcessAsynchParams        = 40,    // Number of FWIMProcessAsynchParam blocks created and queued
  214. // end of fix stuff
  215.  
  216. // Isoch context stuff is hardwired to 1 receive and 1 transmit context for now
  217.     kITContext0                        = 0,    // isoch transmit context 0
  218.     kIRContext0                        = 0,    // isoch receive context 0
  219.     
  220.     kIsochReceiveDMA                = 2,    //
  221.     kIsochTransmitDMA                = 3,    //
  222.     kNumDMAPorts                    = 2,    // Number of DMA channels.
  223.     kIsochTransmitPort                = 0,    // Transmitting isoch port number.
  224.     kIsochReceivePort                = 1,    // Receiving isoch port number.
  225.  
  226.     kNumDCLInterrupts                = 30    // Number of DCL records allowed in interrupt list
  227.                                             // JKL *** this needs to be handled dynamically
  228. };
  229.  
  230.  
  231. // Strictly speaking, these defs are for the TI PHY TSB21LV03 and a 1394a PHY.
  232. // If OpenHCI is used with another PHY, these constants may change.
  233.  
  234. ////////////////////////////////////////////////////////////////////////////////
  235. //
  236. // Phy registers.
  237. //
  238.  
  239. // swapped bit definitions
  240. enum
  241. {
  242.     kPhyBit0                = bit7,
  243.     kPhyBit1                = bit6,
  244.     kPhyBit2                = bit5,
  245.     kPhyBit3                = bit4,
  246.     kPhyBit4                = bit3,
  247.     kPhyBit5                = bit2,
  248.     kPhyBit6                = bit1,
  249.     kPhyBit7                = bit0
  250. };
  251.  
  252. #define PhyBitRange(start, end)                        \
  253. (                                                    \
  254.     (((((UInt32) 0xFF) << (start)) & 0xFF) >>        \
  255.      ((start) + (7 - (end)))) <<                    \
  256.     (7 - (end))                                        \
  257. )
  258.  
  259. #define PhyBitRangePhase(start, end)                \
  260.     (7 - end)
  261.  
  262. // Phy register defs.
  263.  
  264. // 1394 (TSB21LV03) PHY with old register set
  265. enum
  266. {
  267.     kPhyPhysicalIDAddress    = 0,
  268.     kPhyPhysicalID            = PhyBitRange (0, 5),
  269.     kPhyPhysicalIDPhase        = PhyBitRangePhase (0, 5),
  270.  
  271.     kPhyRAddress            = 0,
  272.     kPhyR                    = kPhyBit6,
  273.  
  274.     kPhyCPSAddress            = 0,
  275.     kPhyCPS                    = kPhyBit7,
  276.  
  277.     kPhyRHBAddress            = 1,
  278.     kPhyRHB                    = kPhyBit0,
  279.  
  280.     kPhyIBRAddress            = 1,
  281.     kPhyIBR                    = kPhyBit1,
  282.  
  283.     kPhyGCAddress            = 1,
  284.     kPhyGC                    = PhyBitRange (2, 7),
  285.     kPhyGCPhase                = PhyBitRangePhase (2, 7),
  286.  
  287.     kPhySPDAddress            = 2,
  288.     kPhySPD                    = PhyBitRange (0, 1),
  289.     kPhySPDPhase            = PhyBitRangePhase (0, 1),
  290.  
  291.     kPhyNPAddress            = 2,
  292.     kPhyNP                    = PhyBitRange (3, 7),
  293.     kPhyNPPhase                = PhyBitRangePhase (3, 7),
  294.  
  295.     kPhyPortStatusAddress    = 3,
  296.     kPhyAStat                = PhyBitRange (0, 1),
  297.     kPhyAStatPhase            = PhyBitRangePhase (0, 1),
  298.  
  299.     kPhyBStat                = PhyBitRange (2, 3),
  300.     kPhyBStatPhase            = PhyBitRangePhase (2, 3),
  301.  
  302.     kPhyPortStatus            = PhyBitRange (4, 5),
  303.     kPhyPortStatusPhase        = PhyBitRangePhase (4, 5),
  304.     kPhyCh                    = kPhyBit4,
  305.     kPhyCon                    = kPhyBit5,
  306.  
  307.     kPhyCAddress            = 6,
  308.     kPhyC                    = kPhyBit7
  309. };
  310.  
  311.  
  312.  
  313. // 1394a (TSB41LV06) PHY with Extended Register Set 
  314. enum 
  315. {
  316.     kExtPhyPhysicalIDAddress    = 0,
  317.     kExtPhyPhysicalID            = PhyBitRange (0, 5),
  318.     kExtPhyPhysicalIDPhase        = PhyBitRangePhase (0, 5),
  319.  
  320.     kExtPhyRAddress                = 0,
  321.     kExtPhyR                    = kPhyBit6,
  322.  
  323.     kExtPhyCPSAddress            = 0,
  324.     kExtPhyCPS                    = kPhyBit7,
  325.  
  326.     kExtPhyRHBAddress            = 1,
  327.     kExtPhyRHB                    = kPhyBit0,
  328.  
  329.     kExtPhyIBRAddress            = 1,
  330.     kExtPhyIBR                    = kPhyBit1,
  331.  
  332.     kExtPhyGCAddress            = 1,
  333.     kExtPhyGC                    = PhyBitRange (2, 7),
  334.     kExtPhyGCPhase                = PhyBitRangePhase (2, 7),
  335.     
  336.     kExtPhyExtAddress            = 2,
  337.     kExtPhyExt                    = PhyBitRange (0, 2),
  338.     kExtPhyExtPhase                = PhyBitRangePhase (0, 2),
  339.     
  340.     kExtPhyNPAddress            = 2,
  341.     kExtPhyNP                    = PhyBitRange (3, 7),
  342.     kExtPhyNPPhase                = PhyBitRangePhase (3, 7),
  343.  
  344.     kExtPhySPDAddress            = 3,
  345.     kExtPhySPD                    = PhyBitRange (0, 1),
  346.     kExtPhySPDPhase                = PhyBitRangePhase (0, 1),
  347.     
  348.     kExtPhyLinkAddress            = 4,
  349.     kExtPhyLink                    = kPhyBit0,
  350.  
  351.     kExtPhyCntdAddress            = 4,
  352.     kExtPhyCntd                    = kPhyBit1,
  353.  
  354.     kExtPhyDlyAddress            = 4,
  355.     kExtPhyDly                    = PhyBitRange (2, 3),
  356.     kExtPhyDlyPhase                = PhyBitRangePhase (2, 3),
  357.  
  358.     kExtPhyIRAddress            = 4,
  359.     kExtPhyIR                    = kPhyBit4,
  360.  
  361.     kExtPhyPwrAddress            = 4,
  362.     kExtPhyPwr                    = PhyBitRange (5, 7),
  363.     kExtPhyPwrPhase                = PhyBitRangePhase (5, 7),
  364.  
  365.     kExtPhyISBRAddress            = 5,
  366.     kExtPhyISBR                    = kPhyBit1,
  367.  
  368.     kExtPhyCTOIAddress            = 5,
  369.     kExtPhyCTOI                    = kPhyBit2,
  370.  
  371.     kExtPhyCPSIAddress            = 5,
  372.     kExtPhyCPSI                    = kPhyBit3,
  373.  
  374.     kExtPhySTOIAddress            = 5,
  375.     kExtPhySTOI                    = kPhyBit4,
  376.  
  377.     kExtPhyDPSIAddress            = 5,
  378.     kExtPhyDPSI                    = kPhyBit5,
  379.  
  380.     kExtPhyEAAAddress            = 5,
  381.     kExtPhyEAA                    = kPhyBit6,
  382.  
  383.     kExtPhyEMSCAddress            = 5,
  384.     kExtPhyEMSC                    = kPhyBit7,
  385.  
  386.     kExtPhyPingAddres            = 6,
  387.     kExtPhyPing                    = PhyBitRange (0, 7),
  388.     kExtPhyPingPhase            = PhyBitRangePhase (0, 7),
  389.     
  390.     kExtPhyPortAddres            = 7,
  391.     kExtPhyPort                    = PhyBitRange (3, 7),
  392.     kExtPhyPortPhase            = PhyBitRangePhase (3, 7),
  393.     
  394.     kExtPhyAStatnAddress        = 8,
  395.     kExtPhyAStatn                = PhyBitRange (0, 1),
  396.     kExtPhyAStatnPhase            = PhyBitRangePhase (0, 1),
  397.  
  398.     kExtPhyBStatnAddress        = 8,
  399.     kExtPhyBStatn                = PhyBitRange (2, 3),
  400.     kExtPhyBStatnPhase            = PhyBitRangePhase (2, 3),
  401.  
  402.     kExtPhyPortStatusnAddress    = 8,
  403.     kExtPhyPortStatusn            = PhyBitRange (4, 5),
  404.     kExtPhyPortStatusnPhase        = PhyBitRangePhase (4, 5),
  405.  
  406.     kExtPhyChnAddress            = 8,
  407.     kExtPhyChn                    = kPhyBit4,
  408.  
  409.     kExtPhyConnAddress            = 8,
  410.     kExtPhyConn                    = kPhyBit5,
  411.  
  412.     kExtPhyBiasnAddress            = 8,
  413.     kExtPhyBiasn                = kPhyBit6,
  414.  
  415.     kExtPhyDisnAddress            = 8,
  416.     kExtPhyDisn                    = kPhyBit7,
  417.  
  418.     kExtPhyPeerSpdnAddress        = 9,
  419.     kExtPhyPeerSpdn                = PhyBitRange (0, 1),
  420.     kExtPhyPeerSpdnPhase        = PhyBitRangePhase (0, 1),
  421.  
  422.     kExtPhyInvalidAddress        = 10
  423. };
  424.  
  425.  
  426. // OHCI DMA descriptor fields
  427.  
  428. enum
  429. {
  430.     kTCodeSelfID                = 16
  431. };
  432.  
  433. enum
  434. {
  435.     kPacketTCode                = OHCIBitRange(4, 7),
  436.     kPacketTCodePhase            = OHCIBitRangePhase(4, 7),
  437.  
  438.     kAsynchRt                    = OHCIBitRange(8, 9),
  439.     kAsynchRtPhase                = OHCIBitRangePhase(8, 9),
  440.  
  441.     kAsynchTLabel                = OHCIBitRange(10, 15),
  442.     kAsynchTLabelPhase            = OHCIBitRangePhase(10, 15),
  443.  
  444.     kAsynchSpd                    = OHCIBitRange(16, 18),
  445.     kAsynchSpdPhase                = OHCIBitRangePhase(16, 18),
  446.  
  447.     kAsynchSrcBusID                = bit23,
  448.  
  449.     kAsynchDestinationOffsetHigh        = OHCIBitRange(0, 15),
  450.     kAsynchDestinationOffsetHighPhase    = OHCIBitRangePhase(0, 15),
  451.  
  452.     kAsynchDestinationID                = OHCIBitRange(16, 31),
  453.     kAsynchDestinationIDPhase            = OHCIBitRangePhase(16, 31),
  454.  
  455.     kAsynchDestinationOffsetLow            = OHCIBitRange(0, 31),
  456.     kAsynchDestinationOffsetLowPhase    = OHCIBitRangePhase(0, 31),
  457.  
  458.     kAsynchDataLength            = OHCIBitRange(16, 31),
  459.     kAsynchDataLengthPhase        = OHCIBitRangePhase(16, 31),
  460.  
  461.     kAsynchRCode                = OHCIBitRange(12, 15),
  462.     kAsynchRCodePhase            = OHCIBitRangePhase(12, 15)
  463. };
  464.  
  465. enum
  466. {
  467.     kIsochTCode                    = OHCIBitRange (4, 7),
  468.     kIsochTCodePhase            = OHCIBitRangePhase (4, 7),
  469.  
  470.     kIsochTxChannel                = OHCIBitRange (8, 13),
  471.     kIsochTxChannelPhase        = OHCIBitRangePhase (8, 13),
  472.  
  473.     kIsochTag                    = OHCIBitRange (14, 15),
  474.     kIsochTagPhase                = OHCIBitRangePhase (14, 15),
  475.  
  476.     kIsochTxSpeed                = OHCIBitRange (16, 18),
  477.     kIsochTxSpeedPhase            = OHCIBitRangePhase (16, 18),
  478.  
  479.     kIsochTxDataLength            = OHCIBitRange (16, 31),
  480.     kIsochTxDataLengthPhase        = OHCIBitRangePhase (16, 31)
  481. };
  482.  
  483. struct OHCIDMADescriptorStruct
  484. {
  485.     UInt32                        descriptorField[4];
  486. };
  487. typedef struct OHCIDMADescriptorStruct        DMADescriptor, *DMADescriptorPtr;
  488.  
  489.  
  490. // Constants used in DMA descriptors
  491. enum
  492. {
  493.     kOutputMoreCmd                = 0,
  494.     kOutputMoreKey                = 0,
  495.     kOutputMoreImmCmd            = 0,
  496.     kOutputMoreImmKey            = 2,
  497.     kOutputLastCmd                = 1,
  498.     kOutputLastKey                = 0,
  499.     kInterruptOnError            = 1,
  500.     kInterruptAlways            = 3,
  501.     kInterruptBadAck            = 1,
  502.     kInterruptNever                = 0,
  503.     kOutputMoreBranch            = 0,
  504.     kOutputLastBranch            = 3,
  505.     kOutputLastImmCmd            = 1,
  506.     kOutputLastImmKey            = 2,
  507.     kInputMoreCmd                = 2,
  508.     kInputMoreKey                = 0,
  509.     kInputLastCmd                = 3,
  510.     kInputLastKey                = 0,
  511.     kInputMoreBranch            = 3,
  512.     kBranchAlways                = 3,
  513.     
  514.     kDMACommand                    = OHCIBitRange(28, 31),
  515.     kDMACommandPhase            = OHCIBitRangePhase(28, 31),
  516.     kDMAInputStatus                = bit27,
  517.     kDMAKey                        = OHCIBitRange(24, 26),
  518.     kDMAKeyPhase                = OHCIBitRangePhase(24, 26),
  519.     kDMAPing                    = bit23,
  520.     kDMAInterrupt                = OHCIBitRange(20, 21),
  521.     kDMAInterruptPhase            = OHCIBitRangePhase(20, 21),
  522.     kDMABranch                    = OHCIBitRange(18, 19),
  523.     kDMABranchPhase                = OHCIBitRangePhase(18, 19),
  524.     kDMAReqCount                = OHCIBitRange(0, 15),
  525.     kDMAReqCountPhase            = OHCIBitRangePhase(0, 15),
  526.     kDMAResCount                = OHCIBitRange(0, 15),
  527.     kDMAResCountPhase            = OHCIBitRangePhase(0, 15),
  528.     kDMATransferStatus            = OHCIBitRange(16, 31),
  529.     kDMATransferStatusPhase        = OHCIBitRangePhase(16, 31),
  530.     kDMATimeStamp                = OHCIBitRange(0, 15),
  531.     kDMATimeStampPhase            = OHCIBitRangePhase(0, 15)
  532. };
  533.  
  534. // DMA context fields
  535. enum
  536. {
  537.     kDMAEventCode                = OHCIBitRange(0, 4),
  538.     kDMAEventCodePhase            = OHCIBitRangePhase(0, 4),
  539.     kDMASpeed                    = OHCIBitRange(5, 7),
  540.     kDMASpeedPhase                = OHCIBitRangePhase(5, 7),
  541.     kDMAActive                    = bit10,
  542.     kDMADead                    = bit11,
  543.     kDMAWake                    = bit12,
  544.     kDMARun                        = bit15,
  545.  
  546. // IR DMA context fields
  547.     kIRDMAMultiChanMode            = bit28,
  548.     kIRDMACycleMatchEnable        = bit29,
  549.     kIRDMAIsochHeader            = bit30,
  550.     kIRDMABufferFill            = bit31,
  551.  
  552. // IT DMA context fields
  553.     kITDMACycleMatch            = OHCIBitRange(16, 30),
  554.     kITDMACycleMatchPhase        = OHCIBitRangePhase(16, 30),
  555.     kITDMACycleMatchEnable        = bit31
  556. };
  557.  
  558. // IR DMA match fields
  559. enum
  560. {
  561.     kIRDMAChannelNumber            = OHCIBitRange(0, 5),
  562.     kIRDMAChannelNumberPhase    = OHCIBitRangePhase(0, 5),
  563.     kIRDMATag1SyncFilter        = bit6,
  564.     kIRDMASync                    = OHCIBitRange(8, 11),
  565.     kIRDMASyncPhase                = OHCIBitRangePhase(8, 11),
  566.     kIRDMACycleMatch            = OHCIBitRange(12, 26),
  567.     kIRDMACycleMatchPhase        = OHCIBitRangePhase(12, 26),
  568.     kIRDMATag0                    = bit28,
  569.     kIRDMATag1                    = bit29,
  570.     kIRDMATag2                    = bit30,
  571.     kIRDMATag3                    = bit31
  572. };
  573.  
  574.  
  575. struct DMAContextStruct
  576. {
  577.     volatile UInt32                    controlSet;
  578.     volatile UInt32                    controlClear;
  579.     volatile UInt32                    reserved;
  580.     volatile UInt32                    commandPtr;
  581. };
  582. typedef struct DMAContextStruct        DMAContext,
  583.                                     *DMAContextPtr;
  584.     
  585. struct IRDMAContextStruct
  586. {
  587.     volatile UInt32                    controlSet;
  588.     volatile UInt32                    controlClear;
  589.     volatile UInt32                    reserved0;
  590.     volatile UInt32                    commandPtr;
  591.     volatile UInt32                    match;
  592.     volatile UInt32                    reserved1;
  593.     volatile UInt32                    reserved2;
  594.     volatile UInt32                    reserved3;
  595. };
  596. typedef struct IRDMAContextStruct    IRDMAContext,
  597.                                     *IRDMAContextPtr;
  598.     
  599.  
  600. // OHCI register file
  601.  
  602. struct OHCIRegistersStruct
  603. {
  604.     volatile UInt32                version;
  605.     volatile UInt32                guid_rom;
  606.     volatile UInt32                atRetries;
  607.     volatile UInt32                csrData;
  608.     volatile UInt32                csrCompare;
  609.     volatile UInt32                csrControl;
  610.     volatile UInt32                configROMHdr;
  611.     volatile UInt32                busID;
  612.     volatile UInt32                busOptions;
  613.     volatile UInt32                guidHi;
  614.     volatile UInt32                guidLo;
  615.     volatile UInt32                reserved0;
  616.     volatile UInt32                reserved1;
  617.     volatile UInt32                configROMMap;
  618.     volatile UInt32                postedWriteAddressLo;
  619.     volatile UInt32                postedWriteAddressHi;
  620. // 0x040
  621.     volatile UInt32                vendorID;
  622.     volatile UInt32                reserved2;
  623.     volatile UInt32                reserved3;
  624.     volatile UInt32                reserved4;
  625.     volatile UInt32                hcControlSet;
  626.     volatile UInt32                hcControlClear;
  627.     volatile UInt32                reserved5;
  628.     volatile UInt32                reserved6;
  629.     volatile UInt32                reserved7;
  630.     volatile UInt32                selfIDBuffer;
  631.     volatile UInt32                selfIDCount;
  632.     volatile UInt32                reserved8;
  633.     volatile UInt32                irMultiChanMaskHiSet;
  634.     volatile UInt32                irMultiChanMaskHiClear;
  635.     volatile UInt32                irMultiChanMaskLoSet;
  636.     volatile UInt32                irMultiChanMaskLoClear;
  637. // 0x080
  638.     volatile UInt32                intEventSet;
  639.     volatile UInt32                intEventClear;
  640.     volatile UInt32                intMaskSet;
  641.     volatile UInt32                intMaskClear;
  642.     volatile UInt32                isochTxIntEventSet;
  643.     volatile UInt32                isochTxIntEventClear;
  644.     volatile UInt32                isochTxIntMaskSet;
  645.     volatile UInt32                isochTxIntMaskClear;
  646.     volatile UInt32                isochRxIntEventSet;
  647.     volatile UInt32                isochRxIntEventClear;
  648.     volatile UInt32                isochRxIntMaskSet;
  649.     volatile UInt32                isochRxIntMaskClear;
  650.     volatile UInt32                reserved9[11];
  651. // 0x0DC
  652.     volatile UInt32                fairnessControl;
  653.     volatile UInt32                linkControlSet;
  654.     volatile UInt32                linkControlClear;
  655.     volatile UInt32                nodeID;
  656.     volatile UInt32                phyControl;
  657.     volatile UInt32                isochCycleTimer;
  658.     volatile UInt32                reserved10;
  659.     volatile UInt32                reserved11;
  660.     volatile UInt32                reserved12;
  661. // 0x100
  662.     volatile UInt32                asynchRequestFilterHiSet;
  663.     volatile UInt32                asynchRequestFilterHiClear;
  664.     volatile UInt32                asynchRequestFilterLoSet;
  665.     volatile UInt32                asynchRequestFilterLoClear;
  666.     volatile UInt32                physicalRequestFilterHiSet;
  667.     volatile UInt32                physicalRequestFilterHiClear;
  668.     volatile UInt32                physicalRequestFilterLoSet;
  669.     volatile UInt32                physicalRequestFilterLoClear;
  670.     volatile UInt32                physicalUpperBound;
  671.     volatile UInt32                reserved13[23];
  672. // 0x180
  673.     DMAContext                    asynchRequestTxContext;
  674.     volatile UInt32                reserved14[4];
  675.     DMAContext                    asynchResponseTxContext;
  676.     volatile UInt32                reserved15[4];
  677.     DMAContext                    asynchRequestRxContext;
  678.     volatile UInt32                reserved16[4];
  679.     DMAContext                    asynchResponseRxContext;
  680.     volatile UInt32                reserved17[4];
  681. // 0x200
  682.     DMAContext                    isochTxContext[32];
  683.     IRDMAContext                isochRxContext[32];
  684. };
  685. typedef struct OHCIRegistersStruct
  686.                                 OHCIRegisters,
  687.                                 *OHCIRegistersPtr;
  688.  
  689.  
  690. // Enums for selected registers, etc.
  691.  
  692. // Version register
  693.  
  694. enum
  695. {
  696.     kGUID_ROM                    = bit24,
  697.     kVersion                    = OHCIBitRange(16, 23),
  698.     kVersionPhase                = OHCIBitRangePhase(16, 23),
  699.     kRevision                    = OHCIBitRange(0, 7),
  700.     kRevisionPhase                = OHCIBitRangePhase(0, 7)
  701. };
  702.  
  703.  
  704. // GUID ROM register
  705.  
  706. enum
  707. {
  708.     kAddrReset                    = bit31,
  709.     kRdStart                    = bit25
  710. //
  711. //    JKL *** rdData is also defined as bits 16-23 in the phy register
  712. //    kRdData                        = OHCIBitRange(16, 23),
  713. //    kRdDataPhase                = OHCIBitRangePhase(16, 23)
  714. };
  715.  
  716.  
  717. // Asynch Transmit retry register
  718.  
  719. enum
  720. {
  721.     kSecondLimit                = OHCIBitRange(29, 31),
  722.     kSecondLimitPhase            = OHCIBitRangePhase(29, 31),
  723.     kCycleLimit                    = OHCIBitRange(16, 28),
  724.     kCycleLimitPhase            = OHCIBitRangePhase(16, 28),
  725.     kMaxPhysRespRetries            = OHCIBitRange(8, 11),
  726.     kMaxPhysRespRetriesPhase    = OHCIBitRangePhase(8, 11),
  727.     kMaxATRespRetries            = OHCIBitRange(4, 7),
  728.     kMaxATRespRetriesPhase        = OHCIBitRangePhase(4, 7),
  729.     kMaxATReqRetries            = OHCIBitRange(0, 3),
  730.     kMaxATReqRetriesPhase        = OHCIBitRangePhase(0, 3)
  731. };
  732.  
  733.  
  734. // CSR Control register
  735.  
  736. enum
  737. {
  738.     kCSRDone                    = kBit31,
  739.     kCSRSel                        = OHCIBitRange(0, 1),
  740.     kCSRSelPhase                = OHCIBitRangePhase(0, 1),
  741.     kCHANNELS_AVAILABLE_LO        = 3,
  742.     kCHANNELS_AVAILABLE_HI        = 2,
  743.     kBANDWIDTH_AVAILABLE        = 1,
  744.     kBUS_MANAGER_ID                = 0
  745. };
  746.  
  747.  
  748. // Config ROM Header register
  749.  
  750. enum
  751. {
  752.     kInfo_Length                = OHCIBitRange(24, 31),
  753.     kInfo_Length_Phase            = OHCIBitRangePhase(24, 31),
  754.     kCRC_Length                    = OHCIBitRange(16, 23),
  755.     kCRC_Length_Phase            = OHCIBitRangePhase(16, 23),
  756.     kROM_CRC_Value                = OHCIBitRange(0, 15),
  757.     kROM_CRC_Value_Phase        = OHCIBitRangePhase(0, 15)
  758. };
  759.  
  760.  
  761. // Bus Options register
  762.  
  763. enum
  764. {
  765.     kIRMC                        = bit31,        // isochronous resource maanger capable
  766.     kCMC                        = bit30,        // cycle master capable
  767.     kISC                        = bit29,        // isochronous support capable
  768.     kBMC                        = bit28,        // bus manager capable
  769.     kPMC                        = bit27,        // power management capable
  770.     kCyc_Clk_Acc                = OHCIBitRange(16, 23),    // cycle clock accuracy
  771.     kCyc_Clk_Acc_Phase            = OHCIBitRangePhase(16, 23),
  772.     kMax_Rec                    = OHCIBitRange(12, 15),    // max receive packet size
  773.     kMax_Rec_Phase                = OHCIBitRangePhase(12, 15),
  774.     kG                            = OHCIBitRange(6, 7),        // generation counter
  775.     kG_Phase                    = OHCIBitRangePhase(6, 7),
  776.     kLink_Spd                    = OHCIBitRange(0, 2),        // cycle clock accuracy
  777.     kLink_Spd_Phase                = OHCIBitRangePhase(0, 2)
  778. };
  779.  
  780.  
  781. // Config ROM Mapping register
  782.  
  783. enum
  784. {
  785.     kConfigROMAddr                = OHCIBitRange(10, 31),
  786.     kConfigROMAddrPhase            = OHCIBitRangePhase(10, 31)
  787. };
  788.  
  789.  
  790. // Host Controller Control register
  791.  
  792. enum
  793. {
  794.     kNoByteSwapData                = bit30,
  795.     kProgramPhyEnable            = bit23,
  796.     kAPhyEnhanceEnable            = bit22,
  797.     kLPS                        = bit19,
  798.     kPostedWriteEnable            = bit18,
  799.     kLinkEnable                    = bit17,
  800.     kSoftReset                    = bit16
  801. };
  802.  
  803.  
  804. // Self ID Count register
  805.  
  806. enum
  807. {
  808.     kSelfIDError                = bit31,
  809.     kSelfIDGen                    = OHCIBitRange(16, 23),
  810.     kSelfIDGenPhase                = OHCIBitRangePhase(16, 23),
  811.     kSelfIDSize                    = OHCIBitRange(2, 10),
  812.     kSelfIDSizePhase            = OHCIBitRangePhase(2, 10)
  813. };
  814.  
  815.  
  816. // Interrupt Event register
  817.  
  818. enum
  819. {
  820.     kMasterIntEnable            = bit31,
  821.     kPhyRegRcvd                    = bit26,
  822.     kCycleTooLong                = bit25,
  823.     kUnrecoverableError            = bit24,
  824.     kCycleInconsistent            = bit23,
  825.     kCycleLost                    = bit22,
  826.     kCycle64Seconds                = bit21,
  827.     kCycleSynch                    = bit20,
  828.     kPhyInt                        = bit19,
  829.     kBusReset                    = bit17,
  830.     kSelfIDComplete                = bit16,
  831.     kLockRespErr                = bit9,
  832.     kPostedWriteErr                = bit8,
  833.     kIsochRx                    = bit7,
  834.     kIsochTx                    = bit6,
  835.     kRSPkt                        = bit5,
  836.     kRQPkt                        = bit4,
  837.     kARRS                        = bit3,
  838.     kARRQ                        = bit2,
  839.     kRespTxComplete                = bit1,
  840.     kReqTxComplete                = bit0
  841. };
  842.  
  843.  
  844. // some missing
  845.  
  846. // GPIO Control Register A and B
  847.  
  848. enum
  849. {
  850.     kOHCIGPIO_OUT_EN0            = bit0,
  851.     kOHCIGPIO_POL_OUT0            = bit2,
  852.     kOHCIGPIO_SRC0                = OHCIBitRange(8, 12),
  853.     kOHCIGPIO_SRC0Phase            = OHCIBitRangePhase(8, 12),
  854.  
  855.     kOHCIGPIO_OUT_EN1            = bit16,
  856.     kOHCIGPIO_POL_OUT1            = bit18,
  857.     kOHCIGPIO_SRC1                = OHCIBitRange(24, 28),
  858.     kOHCIGPIO_SRC1Phase            = OHCIBitRangePhase(24, 28),
  859.  
  860.     kOHCIGPIO_OUT_EN2            = bit0,
  861.     kOHCIGPIO_POL_OUT2            = bit2,
  862.     kOHCIGPIO_SRC2                = OHCIBitRange(8, 12),
  863.     kOHCIGPIO_SRC2Phase            = OHCIBitRangePhase(8, 12),
  864.  
  865.     kOHCIGPIO_OUT_EN3            = bit16,
  866.     kOHCIGPIO_POL_OUT3            = bit18,
  867.     kOHCIGPIO_SRC3                = OHCIBitRange(24, 28),
  868.     kOHCIGPIO_SRC3Phase            = OHCIBitRangePhase(24, 28)
  869.  
  870. };
  871.  
  872. // DMA OpenHCI events
  873.  
  874. enum
  875. {
  876.     kEvtNoStatus                = 0,
  877.     kEvtLongPacket                = 2,
  878.     kEvtMissingAck                = 3,
  879.     kEvtUnderrun                = 4,
  880.     kEvtOverrun                    = 5,
  881.     kEvtDescriptorRead            = 6,
  882.     kEvtDataRead                = 7,
  883.     kEvtDataWrite                = 8,
  884.     kEvtBusReset                = 9,
  885.     kEvtTimeout                    = 10,
  886.     kEvtTCodeErr                = 11,
  887.     kEvtUnknown                    = 14,
  888.     kEvtFlushed                    = 15,
  889.     
  890.     kEventType                    = bit4
  891. };
  892.  
  893. // Link Control register
  894.  
  895. enum
  896. {
  897.     kCycleSource                = bit22,
  898.     kCycleMaster                = bit21,
  899.     kCycleTimerEnable            = bit20,
  900.     kRcvPhyPkt                    = bit10,
  901.     kRcvSelfID                    = bit9,
  902.     kA_Phy                        = bit4
  903. };
  904.  
  905.  
  906. // Node ID and Status register
  907.  
  908. enum
  909. {
  910.     kIDValid                    = bit31,
  911.     kRoot                        = bit30,
  912.     kCPS                        = bit27,
  913.     kBusNumber                    = OHCIBitRange(6, 15),
  914.     kBusNumberPhase                = OHCIBitRangePhase(6,15),
  915.     kNodeNumber                    = OHCIBitRange(0, 5),
  916.     kNodeNumberPhase            = OHCIBitRangePhase(0, 5),
  917.     kBusNumberNodeNumber        = OHCIBitRange(0, 15),
  918.     kBusNumberNodeNumberPhase    = OHCIBitRangePhase(0, 15)
  919. };
  920.  
  921.  
  922. // Phy Control register
  923.  
  924. enum
  925. {
  926.     kPhyRdDone                    = bit31,
  927.     kPhyRdAddr                    = OHCIBitRange(24, 27),
  928.     kPhyRdAddrPhase                = OHCIBitRangePhase(24, 27),
  929.     kPhyRdData                    = OHCIBitRange(16, 23),
  930.     kPhyRdDataPhase                = OHCIBitRangePhase(16, 23),
  931.     kPhyRdReg                    = bit15,
  932.     kPhyWrReg                    = bit14,
  933.     kPhyRegAddr                    = OHCIBitRange(8, 11),
  934.     kPhyRegAddrPhase            = OHCIBitRangePhase(8, 11),
  935.     kPhyWrData                    = OHCIBitRange(0, 7),
  936.     kPhyWrDataPhase                = OHCIBitRangePhase(0, 7)
  937. };
  938.  
  939.  
  940. // Cycle Timer register
  941.  
  942. enum
  943. {
  944.     kCycleSeconds                = OHCIBitRange(25, 31),
  945.     kCycleSecondsPhase            = OHCIBitRangePhase(25, 31),
  946.     kCycleCount                    = OHCIBitRange(12, 24),
  947.     kCycleCountPhase            = OHCIBitRangePhase(12, 24),
  948.     kCycleOffset                = OHCIBitRange(0, 11),
  949.     kCycleOffsetPhase            = OHCIBitRangePhase(0, 11)
  950. };
  951.  
  952.  
  953. // Defs for pending FWIM commands.
  954.  
  955. enum
  956. {
  957.     kPendingFWIMCommandBusy    = 1
  958. };
  959.  
  960.  
  961. struct IsochPortDataStruct
  962. {
  963.     DCLProgramID                dclProgramID,            // ID of DCL program we're using.
  964.                                 originalDCLProgramID,    // Original DCL program ID.
  965.                                 translatedDCLProgramID;    // Translated DCL program ID.
  966.     UInt32                        channelNum;                // Isoch channel number used for this port.
  967.     UInt32                        speed;                    // Speed of this port.
  968.     Boolean                        talking;                // True if port is for talking.
  969. };
  970. typedef struct IsochPortDataStruct
  971.                                 IsochPortData,
  972.                                 *IsochPortDataPtr;
  973.  
  974. // put this typedef up here so it is available to the next two definitions
  975. typedef struct OHCIFWIMDataStruct        OHCIFWIMData, *FWIMDataPtr;
  976.  
  977. typedef struct AsynchRxDMADataStruct
  978.                                 AsynchRxDMAData,
  979.                                 *AsynchRxDMADataPtr;
  980. struct AsynchRxDMADataStruct
  981. {
  982.     AsynchRxDMADataPtr            pNextAsynchRxDMAData;    // Logical pointer to next descriptor.
  983.     FWIMDataPtr                    pFWIMData;                // Pointer to OHCI FWIM data.
  984.     DMADescriptorPtr            pDMA;                    // Logical pointer to descriptor.
  985.     Ptr                            pDMAPhysical;            // Physical pointer to descriptor.
  986.     Ptr                            packetBuffer;            // Logical packet buffer of DMA.
  987.     UInt32                        packetStart;            // Index into packet buffer for start of next packet
  988. };
  989.  
  990. struct FWIMProcessAsynchParamsQElem
  991. {
  992.     QElemPtr                     qLink;                    // queue link in header
  993.     SInt16                         qType;                    // type
  994.     FWIMDataPtr                    pFWIMData;                // Pointer to OHCI FWIM data.
  995.     AsynchRxDMADataPtr            pAsynchRxDMAData;        // DMA data record
  996.     FWIMProcessAsynchParams     fwimProcessAsynchParams;    // the process params data
  997.     Boolean                        DMAFull;                // true if the DMA descriptor is complete
  998. };
  999. typedef struct FWIMProcessAsynchParamsQElem
  1000.                                 FWIMProcessAsynchParamsQElem,
  1001.                                 *FWIMProcessAsynchParamsQElemPtr;
  1002.  
  1003. typedef struct AsynchTxDMADataStruct
  1004.                                 AsynchTxDMAData,
  1005.                                 *AsynchTxDMADataPtr;
  1006. struct AsynchTxDMADataStruct                            // information for a transmit desciptor block, not a single descriptor
  1007. {                                                        // each one of these holds up to 8 descriptors, 128 bytes
  1008.     AsynchTxDMADataPtr            pNextAsynchTxDMAData;    // Logical pointer to next descriptor.
  1009.     FWIMDataPtr                    pFWIMData;                // Pointer to OHCI FWIM data.
  1010.     DMADescriptorPtr            pDMA;                    // Logical pointer to descriptor.
  1011.     Ptr                            pDMAPhysical;            // Physical pointer to descriptor.
  1012.     IOPreparationTable            ioPrep;                    // Used for prep'ing transmit buffers.
  1013.     UInt32                        numDMADescriptors;        // Number of descriptors that make up this descriptor block
  1014. };
  1015.  
  1016. typedef struct DCLProgramInterruptStruct
  1017.                                 DCLProgramInterrupt,
  1018.                                 *DCLProgramInterruptPtr;
  1019.  
  1020. struct DCLProgramInterruptStruct
  1021. {
  1022.     DCLCommandPtr                pDCLCommand;            // Pointer to DCL command that caused interrupt
  1023.     Boolean                        pendingInterrupt;        // true if DCL needs interrupt processing
  1024. };
  1025.  
  1026. // Private data structure for OHCIFWIM - one per OHCI
  1027.  
  1028. struct OHCIFWIMDataStruct
  1029. {
  1030.     DCLProgramInterrupt            pDCLInterruptList[kNumDMAPorts][kNumDCLInterrupts];    // List of DCLs that cause an interrupt, one list for each port, JKL *** hardwired to 2
  1031.     UInt32                        numDCLInterrupts[kNumDMAPorts];    // count of above DCL interrupts
  1032.                                                                 // JKL *** not good, fix this
  1033.     
  1034.     Ptr                            selfIDBuf;                        // buffer for self ids ...
  1035.     PhysicalAddress                selfIDBufPhys;                    // and its physical address
  1036.  
  1037.     Ptr                            pActiveConfigROM;                // logic address of active config ROM buffer
  1038.     PhysicalAddress                pActiveConfigROMPhys;            // Physical address of active config ROM buffer
  1039.     Ptr                            pNextConfigROM;                    // logic address of next config ROM buffer
  1040.     PhysicalAddress                pNextConfigROMPhys;                // Physical address of next config ROM buffer
  1041.  
  1042.     UInt32                        isochContexts;                    // number of isoch contexts implemented in the OpenHCI link    
  1043.     QHdrPtr                        pFWIMProcessAsynchParamsQueue;    // queue for 
  1044.     PhysicalAddress                fwimDataPhys;                    // Physical address of this struct
  1045.     IOPreparationTable            fwimDataIOPrep;                    // ioPrep data for this struct
  1046.     FWIMID                        fwimID;                            // ID for this FWIM
  1047.     RegEntryID                    FWIMRegEntryID;                    // Name registry ID for TI card.
  1048.     UInt32                        generation;                        // Current bus generation number.
  1049.     Boolean                        generationValid;                // Generation number is valid.
  1050.     Boolean                        root;                            // True if we're root.
  1051.     TimerID                        resetDebounceTimerID;            // TimerID for debouncing resets
  1052.     Boolean                        resetDebounceTimerSet;            // Flag indicating the above timer is running
  1053.     TimerID                        requestTimeoutTimerID;            // TimerID to indicate timeout of a read/write request
  1054.     Boolean                        requestTimeoutTimerSet;            // Flag indicating the above timer is running
  1055.     TimerID                        selfidTimeoutTimerID;            // TimerID to indicate timeout of selfid receive
  1056.     Boolean                        selfidTimeoutTimerSet;            // Flag indicating the above timer is running
  1057.  
  1058.     FWDeferredTaskID            busResetDeferredTaskID;            // Deferred task ID for handling bus resets.
  1059.     Boolean                        busResetDTScheduled;            // True if we've scheduled a DT to handle bus resets.
  1060.     FWDeferredTaskID            selfIDDeferredTaskID;            // Deferred task ID for handling self ids.
  1061.     Boolean                        selfIDDTScheduled;                // True if we've scheduled a DT to handle self ids.
  1062.     FWDeferredTaskID            unrecoverableErrorDeferredTaskID;    // Deferred task ID for handling unrecoverable error interrupts.
  1063.     Boolean                        unrecoverableErrorDTScheduled;        // True if we've scheduled a DT to handle unrecoverable errors.
  1064.     FWDeferredTaskID            asynchReqRxPktDeferredTaskID;    // Deferred task ID for handling received asynch request packets.
  1065.     Boolean                        asynchReqRxPktDTScheduled;        // True if we've sceduled a DT to handle received asynch request packets.
  1066.     FWDeferredTaskID            asynchResRxPktDeferredTaskID;    // Deferred task ID for handling received asynch response packets.
  1067.     Boolean                        asynchResRxPktDTScheduled;        // True if we've sceduled a DT to handle received asynch response packets.
  1068.     FWDeferredTaskID            asynchReqRxDMADeferredTaskID;    // Deferred task ID for handling received asynch request DMA interrupts.
  1069.     Boolean                        asynchReqRxDMADTScheduled;        // True if we've sceduled a DT to handle received asynch request DMA interrupts.
  1070.     FWDeferredTaskID            asynchResRxDMADeferredTaskID;    // Deferred task ID for handling received asynch response DMA interrupts.
  1071.     Boolean                        asynchResRxDMADTScheduled;        // True if we've sceduled a DT to handle received asynch response DMA interrupts.
  1072.     FWDeferredTaskID            isochReceiveDeferredTaskID;        // Deferred task ID for handling received isoch packets.
  1073.     Boolean                        isochReceiveDTScheduled;        // True if we've sceduled a DT to handle received isoch packets.
  1074.     FWDeferredTaskID            isochTransmitDeferredTaskID;    // Deferred task ID for handling transmitted isoch packets.
  1075.     Boolean                        isochTransmitDTScheduled;        // True if we've sceduled a DT to handle transmitted isoch packets.
  1076.     FWDeferredTaskID            asynchReqTxDeferredTaskID;        // Deferred task ID for handling asynch transmit request interrupts.
  1077.     Boolean                        asynchReqTxDTScheduled;            // True if we've sceduled a DT to handle asynch transmit request interrupts.
  1078.     FWDeferredTaskID            asynchResTxDeferredTaskID;        // Deferred task ID for handling asynch transmit response interrupts.
  1079.     Boolean                        asynchResTxDTScheduled;            // True if we've sceduled a DT to handle asynch transmit response interrupts.
  1080.  
  1081.     FWIMCommandParamsPtr        pPendingFWIMCommand;            // Pending FWIM command.
  1082.     OSStatus                    pendingFWIMCommandStatus;        // Internal status of pending FWIM command.
  1083.     FWIMCommandParamsPtr        pPendingFWIMResponseCommand;    // Pending FWIM response command.
  1084.     UInt32                        transactionLabel;                // Label used for current transaction
  1085.     UInt32                        tCode;                            // TCode for current transaction.
  1086.     InterruptSetMember            interruptSetMember;
  1087.     void                        *oldInterruptRefCon;
  1088.     InterruptHandler            oldInterruptHandler;
  1089.     InterruptEnabler            interruptEnabler;
  1090.     InterruptDisabler            interruptDisabler;
  1091.     OHCIRegistersPtr            pOHCIRegisters;                    // Register file
  1092.  
  1093.     Ptr                            asynchRxBuf[kAsynchRxBufs];        // Asynch receive buffers ...
  1094.     Ptr                            asynchRxBufPhys[kAsynchRxBufs];    // and their physical address
  1095.     DMADescriptorPtr            asynchRxDMA;                    // Asynch receive DMA descriptors, block of kAsynchRxBufs
  1096.     Ptr                            asynchRxDMAPhys;                // and their physical address
  1097.     AsynchRxDMADataPtr            asynchRxDMADataList;            // List of data records for asynch receive
  1098.     AsynchRxDMADataPtr            pNextAsynchReqRxDMAData;        // Next asynch receive request DMA to process.
  1099.     AsynchRxDMADataPtr            pLastAsynchReqRxDMAData;        // Last available asynch receive request DMA descriptor.
  1100.     AsynchRxDMADataPtr            pNextAsynchResRxDMAData;        // Next asynch receive response DMA to process.
  1101.     AsynchRxDMADataPtr            pLastAsynchResRxDMAData;        // Last available asynch receive response DMA descriptor.
  1102.     AsynchRxDMADataPtr            pStartAsynchReqRxDMAData;        // DMA data record to start asynch receive request program.
  1103.     AsynchRxDMADataPtr            pStartAsynchResRxDMAData;        // DMA data record to start asynch receive response program.
  1104.     AsynchRxDMADataPtr            pEndAsynchReqRxDMAData;            // DMA data record with buffer at the end of the contiguous buffer space.
  1105.     AsynchRxDMADataPtr            pEndAsynchResRxDMAData;            // DMA data record with buffer at the end of the contiguous buffer space.
  1106.     
  1107.     DMADescriptorPtr            asynchTxDMA;                    // Asynch transmit DMA descriptors ...
  1108.     Ptr                            asynchTxDMAPhys;                // and their physical address
  1109.     AsynchTxDMADataPtr            asynchTxDMADataList;            // List of descriptor block data records for asynch transmit.
  1110.     AsynchTxDMADataPtr            pNextAsynchReqTxDMAData;        // Next asynch transmit request DMA data record to use.
  1111.     AsynchTxDMADataPtr            pFirstAsynchReqTxDMAData;        // First asynch transmit request DMA data record to process.
  1112.     AsynchTxDMADataPtr            pNextAsynchResTxDMAData;        // Next asynch transmit response DMA data record to use.
  1113.     AsynchTxDMADataPtr            pFirstAsynchResTxDMAData;        // First asynch transmit response DMA data record to process.
  1114.     
  1115.     IOPreparationTable            ioPrep;                            // For VM
  1116.     PhysicalAddress                physAddrs[kAsynchRxBufs+20];    // Page table - fix this, arbitrary constant, could allocate exact amount and deallocate
  1117.     IsochPortDataPtr            isochPortDataList[kNumDMAPorts];    // List of isoch port data records.
  1118.     UInt32                        pageSize,                        // Physical page size and shift for VM.
  1119.                                 pageShift;
  1120.  
  1121.     Boolean                        extendedPhyRegs;                // True if we have a 1394a PHY with the extended register set                    
  1122.     UInt32                        phySpeed;                        // Some 400 phys also include their own self-id in self-id buffer but are not extended.
  1123.                                                                 // Use speed for another check to remove self-ids.
  1124.  
  1125.     UInt32                        localSelfIDQuads[8];            // Support lots of ports. Overkill probably
  1126.     UInt8                        selfIDPacketBuffer[2048];        // The actual self-id packets
  1127.     UInt32                        numPHYPorts;                    // Number of ports supported by the PHY
  1128.     UInt32                        *csrROMUpdateClearWhenDone;        // For managing physical CSR ROM updates.
  1129.     SInt32                        busResetCount;                    // counter for synching bus resets with asynch receive
  1130. };
  1131.  
  1132. typedef struct DMAPoolDataStruct
  1133.                                 DMAPoolData,
  1134.                                 *DMAPoolDataPtr;
  1135. struct DMAPoolDataStruct
  1136. {
  1137.     DMAPoolDataPtr                pNextDMAPoolData;            // Link to next DMA pool data record.
  1138.     UInt32                        nextFreeDMA;                // Next free DMA in pool.
  1139.     UInt32                        DMAPoolCount;                // Number of DMA descriptors in pool.
  1140.     DMADescriptorPtr            DMAPoolBase;                // 16-byte-aligned DMA pool base address.
  1141.     UInt32                        DMAPoolBasePhys;            // Physical addr of same
  1142.     IOPreparationTable            ioPrep;                        // For VM
  1143.     PhysicalAddress                physAddrs[1];                // warning, if DMA pools gets larger than a page increment this
  1144. };
  1145.  
  1146.  
  1147. // We create one of these for each DCL command to hold compiler private information:
  1148. struct DCLCompilerDCLDataStruct
  1149. {
  1150.     DMADescriptorPtr            pDMA;                        // pointer to (first) descriptor
  1151.     PhysicalAddress                pDMAPhys;                    // Physical address of same
  1152. };
  1153. typedef struct DCLCompilerDCLDataStruct
  1154.                                 DCLCompilerDCLData,
  1155.                                 *DCLCompilerDCLDataPtr;
  1156.  
  1157. // As we compile DCLs into DMA programs, this structure keeps track of general
  1158. // information.  There is one of these for each program being compiled.
  1159. struct DCLCompilerEngineDataStruct
  1160. {
  1161.     FWIMDataPtr                    pFWIMData;                // Our FWIM data.
  1162.     UInt32                        pStartDMA;                // Physical address of first descriptor block in program, includes Z value.
  1163.     DMAPoolDataPtr                pDMAPoolDataList;        // List of DMA pools allocated for this compiled program.
  1164.     UInt32                        engineGeneration;        // For faster lookups
  1165.     UInt32                        startEvent;                // start event for the DMA program
  1166.     UInt32                        startEventState;        // if start event is cycleMatch, contains cycle count
  1167.     IOPreparationTable            ioPrep;                    // For all buffers/etc
  1168.     DCLCompilerDCLDataPtr        pDCLCompilerDCLData;    // Base of compiler data list
  1169. };
  1170. typedef struct DCLCompilerEngineDataStruct
  1171.                                 DCLCompilerEngineData,
  1172.                                 *DCLCompilerEngineDataPtr;
  1173.  
  1174. // As we compile DCLs into DMA programs, this structure keeps track of DMA-oriented
  1175. // information.  There is one of these for each program being compiled.
  1176. struct DMABuildStateStruct
  1177. {
  1178.     FWIMDataPtr                    pFWIMData;                // Our FWIM data.
  1179.     DCLCompilerEngineDataPtr    pDCLCompilerEngineData;    // Compiler engine data.
  1180.     DMAPoolDataPtr                pDMAPoolDataList;        // List of DMA pools allocated for this build.
  1181.     UInt32                        dmaPortNum;                // DMA port number we're building for.
  1182.     UInt32                        isochChannelNum;        // Isochronous channel number.
  1183.     UInt32                        *pLastBranch;            // unfilled branch from last DMA
  1184.     UInt32                        isochRxDummyQuadPhys;    // dummy quad address used to skip over timeStamp quad for isoch receive
  1185.     UInt16                        tagBits;                // tag bits set by a DCL command
  1186.     UInt16                        syncBits;                // sync bits set by a DCL command
  1187. };
  1188. typedef struct DMABuildStateStruct
  1189.                                 DMABuildState,
  1190.                                 *DMABuildStatePtr;
  1191.  
  1192.  
  1193. #if PRAGMA_ALIGN_SUPPORTED
  1194. #pragma options align=reset
  1195. #endif
  1196.  
  1197. #if PRAGMA_IMPORT_SUPPORTED
  1198. #pragma import off
  1199. #endif
  1200.  
  1201. #ifdef __cplusplus
  1202. }
  1203. #endif
  1204.  
  1205. #endif /* __OHCIFWIM__ */
  1206.